The present invention relates generally to digital electronic circuits, and more particularly relates to domino logic circuits.
Modern integrated circuits are required to perform ever increasing tasks, and at ever increasing operating speeds. The requirement to increase operating speeds has often been met by increasing the clock speed at which a circuit operates. For example, while integrated circuit operation once occurred at clock speeds on the order of 10 to 50 MHz, clock speeds now are often significantly greater than 100 MHz, and in some cases are even on the order of 400 MHz or more.
Increasing clock speeds, however, is not the only method available to circuit designers to increase the speed at which circuit operations occur. Circuit designers have also implemented circuitry which operates in a staged manner, with each stage evaluating over only a portion of a clock cycle and subsequent stages evaluating over subsequent portions of the clock cycle. That is, circuit designers arrange logic operations in a sequential manner, with each logic cell in the sequence providing information to subsequent logic cells in the sequence. These logic cells are evaluated during only a portion of the clock cycle, with subsequent logic cells evaluated in subsequent portions of the clock cycle. These logic cells therefore operate in a domino manner, and are often referred to as domino logic cells. The use of domino logic circuits allows designers to increase the effective speed of logic components without resorting to increasing clock speed.
In order to allow logic cells to evaluate their inputs in less than an entire clock cycle logic cells are often precharged. Precharging the logic cell is accomplished by driving the logic cell either to a mid range or to a high state. Driving the logic cell to a mid-range state allows the logic cell to change state with only a slight change in voltage. Thus the logic cell is able to change state at a faster rate than otherwise would occur. More often, however, the outputs of logic cells are driven to a high state. This is because PMOS transistors generally have a relatively large rise time due to parasitic capacitances. Accordingly, logic cell operation response time may be increased by charging the output to a high level prior to evaluation of the logic cell.
In a single clock cycle, therefore, a logic cell must be precharged, and thereafter allowed to evaluate its inputs. This is often accomplished by precharging the logic cell during one-half of a clock cycle, and allowing the logic cell to evaluate its inputs during the other half of the clock cycle. One constraint of such a methodology, however, is that the logic cell must evaluate and provide its outputs to a subsequent logic cell in one half of the clock cycle. Further, subsequent precharging of the logic cell during the first half of a subsequent clock cycle may modify the outputs of the logic cell. Accordingly, the logic cell should not begin precharging until after the subsequent logic cell has evaluated its inputs.
In order for domino logic circuits to meet such requirements, particularly when the circuits are also operating at high clock speeds, the derivation and use of additional signals based on the output of the logic cell should be kept to a minimum. One such additional signal is a complement of the output signal. Forming a complement of the output signal, using an inverter for example, poses several problems. The additional inverter used to form the output signal complement places a delay in a signal path of an input to the subsequent logic stage, thereby limiting the period in which the logic cell has to evaluate its inputs. Further, this delay effects only the complementary signal path (ignoring fan out related delays), and the output signal path does not include this delay. Accordingly, changes in the output signal during subsequent precharging are not delayed by the inverter in the signal path of the output complement signal. Thus, the period in which the subsequent logic cell may evaluate its input, starting from the time when the complementary output of the logic cell goes valid and ending at the time the effects of precharging propagate to the output signal of the logic cell, is reduced due to the use of the output signal complement.
Therefore, when use of an output signal complement is desired a dual rail, as opposed to signal rail, domino logic design is generally used. Single rail designs generally only have a single output per logic cell. Thus, a single rail design is monotonic in nature. In a dual rail design a first set of logic cells produces a set of signals, and a second set, or rail, of logic cells produces the complements of these signals. Dual rail designs, however, require significantly greater number of gates than a single rail design, resulting in increased chip layout space as well as increased power consumption.
The requirement for increased functionality of integrated circuits, thus, results in a need to decrease the area occupied by logic while also increasing the size of the integrated circuit as a whole. To the extent the need for increased functionality outstrips the ability to decrease gate size and increase chip die size, chip area is placed at a premium. The use of dual rail designs, therefore, impacts the ability of designers to provide increased functionality in integrated circuits.